Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems

The high performance computing architectures are the primary need for the modern devices having compute-intensive applications such as signal and image processing. This paper presents a novel low complexity carry-skip adder design that provides high-speed and consumes low-power making it suitable for the development of high-performance signal processing cores. The proposed adder is derived from the reformulated Boolean expressions that avoid the redundant computations with reduced critical path delay. The proposed architectures are coded in VHDL and synthesized with Synopsys Design Compiler using 65nm CMOS library. Synthesis results demonstrate that the proposed 32-bit carry skip adder reduces the delay, area and power by 10.2%, 13.6% and 8% respectively than the best known carry skip adder. Finally, the proposed 16- and 32-bit adders reduce the area-delay product by 14.4% and 22.5% respectively over the existing adder.