Efficient Implementation of Convolution Encoder and Viterbi Decoder

被引：0

作者：

Soreng, Bineeta ^{[1
]}

Kumar, Saurabh ^{[1
]}

机构：

[1] Natl Inst Technol, Dept Elect & Commun Engn, Rourkela 769008, India

来源：

PROCEEDINGS OF 2013 INTERNATIONAL CONFERENCE ON CIRCUITS, POWER AND COMPUTING TECHNOLOGIES (ICCPCT 2013) | 2013年

关键词：

Convolution Encoder; VHDL; Viterbi Decoder; Stratix IV;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper describes about the Convolution Encoder and Viterbi Decoder algorithm. The main aim is to achieve encoding and decoding rate as per WiMAX standard. Here, Convolution Encoder and Viterbi Decoder of code rate 1/2, constraint length 7; generator polynomial (171,133) has been implemented on EP4SGX70HF35C2 device of Stratix IV family in Altera DE board. Coding style of VHDL is used. The design has been synthesized using Altera Quartus II vl1.0 and has been simulated using ModelSim Altera Starter Edition 6.6d. The comparison results show a large improvement in area.

引用

页码：1270 / 1273

页数：4

共 50 条

[1] Efficient implementation of Convolution Encoder and Viterbi Decoder
[J]. 1600, IEEE Computer Society
[2] Low Power VLSI Implementation of Convolution Encoder and Viterbi Decoder using Verilog HDL
Ramanna, Dasari
Ganesan, V
[J]. BIOSCIENCE BIOTECHNOLOGY RESEARCH COMMUNICATIONS, 2020, 13 (13): : 177 - 184
[3] RTL Design and VLSI Implementation of an efficient Convolutional Encoder and Adaptive Viterbi Decoder
Suganya, G. S.
Kavya, G.
[J]. 2013 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2013, : 494 - 498
[4] Implementation of Convolutional Encoder and Viterbi Decoder using VHDL
Wong, Yin Sweet
Ong, Wen Jian
Chong, Jin Hui
Ng, Chee Kyun
Noordin, Nor Kamariah
[J]. 2009 IEEE STUDENT CONFERENCE ON RESEARCH AND DEVELOPMENT: SCORED 2009, PROCEEDINGS, 2009, : 22 - 25
[5] A FPGA implementation of a parallel Viterbi decoder for block cyclic and convolution codes
Reeve, JS
Amarasinghe, K
[J]. 2004 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-7, 2004, : 2596 - 2599
[6] Efficient Speech Enhancement Using Recurrent Convolution Encoder and Decoder
Karthik, A.
MazherIqbal, J. L.
[J]. WIRELESS PERSONAL COMMUNICATIONS, 2021, 119 (03) : 1959 - 1973
[7] Efficient Speech Enhancement Using Recurrent Convolution Encoder and Decoder
A. Karthik
J. L. MazherIqbal
[J]. Wireless Personal Communications, 2021, 119 : 1959 - 1973
[8] CMOS implementation of Viterbi decoder
Sutagundar, Manjula
Kambalimath, S. G.
Sutagundar, A. V.
[J]. PROCEEDINGS OF THE 6TH WSEAS INTERNATIONAL CONFERENCE ON SYSTEM SCIENCE AND SIMULATION IN ENGINEERING (ICOSSSE '07): SYSTEM SCIENCE AND SIMULATION IN ENGINEERING, 2007, : 280 - +
[9] Efficient Hardware Implementation of Encoder and Decoder for Golay Code
Sarangi, Satyabrata
Banerjee, Swapna
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (09) : 1965 - 1968
[10] RTL Level Implementation of High Speed-Low Power Viterbi Encoder & Decoder
Singh, Pooran
Vishvakarma, Santosh Kr
[J]. 2013 INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE AND TECHNOLOGY (ICIST), 2013, : 345 - 349

← 1 2 3 4 5 →