Efficient Implementation of Convolution Encoder and Viterbi Decoder

被引：0
|
作者：
Soreng, Bineeta [1 ]
Kumar, Saurabh [1 ]
机构：
[1] Natl Inst Technol, Dept Elect & Commun Engn, Rourkela 769008, India
来源：
PROCEEDINGS OF 2013 INTERNATIONAL CONFERENCE ON CIRCUITS, POWER AND COMPUTING TECHNOLOGIES (ICCPCT 2013) | 2013年
关键词：
Convolution Encoder; VHDL; Viterbi Decoder; Stratix IV;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
This paper describes about the Convolution Encoder and Viterbi Decoder algorithm. The main aim is to achieve encoding and decoding rate as per WiMAX standard. Here, Convolution Encoder and Viterbi Decoder of code rate 1/2, constraint length 7; generator polynomial (171,133) has been implemented on EP4SGX70HF35C2 device of Stratix IV family in Altera DE board. Coding style of VHDL is used. The design has been synthesized using Altera Quartus II vl1.0 and has been simulated using ModelSim Altera Starter Edition 6.6d. The comparison results show a large improvement in area.
引用
收藏
页码：1270 / 1273
页数：4
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