Efficient mapping on FPGA of a Viterbi decoder for wireless LANs

被引：5
|
作者：
Angarita, F [1 ]
Perez-Pascual, A [1 ]
Sansaloni, T [1 ]
Valls, J [1 ]
机构：
[1] Univ Politecn Valencia, Dept Ingn Elect, Valencia 46730, Spain
来源：
2005 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS - DESIGN AND IMPLEMENTATION (SIPS) | 2005年
关键词：
D O I：
10.1109/SIPS.2005.1579957
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper an optimized hardware implementation on FPGA of a Viterbi decoder is presented for WLAN. A fixed-point analysis is made and its performance is compared with a soft decision decoding floating point model with CSI weight. Only 6 bits are needed to perform the soft quantification and 7 bits to the CSI, in order to maintain the performance of the floating point model. A normalization method is proposed to increase the throughput of the decoder, being possible to decode 172 Mbps when it is implemented in a Virtex 2 device. Power consumption results of the decoder implementation are presented for Hiperlan/2 maximum rate. Moreover, it has been shown that it is possible to reduce the power consumption disabling the unnecessary hardware depending on the WLAN modes.
引用
收藏
页码：710 / 715
页数：6
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