Low Power VLSI Implementation of Convolution Encoder and Viterbi Decoder using Verilog HDL

Viterbi decoder is considered as one of the widespread error correcting channel decoder of communication devices. The Viterbi decoder is mainly used for decoding the convolution codes. The large amount of trellis transitions increases the computational complexity of the Viterbi decoder. In this paper, the finite state machine based trellis encoding is proposed in the convolutional encoder for minimizing the system complexity. Moreover, the folding transformation is proposed in the Viterbi decoder for minimizing the number of stages processed while decoding the encoded data bits. The main objective of this proposed system is that the reconstruction of original data bits with less errors. The performance of the proposed system is analyzed in terms of number of slice LUT, number of slice register, BRAM, delay and failure rate. In addition, the performance of the proposed method is evaluated with the duplication with comparison based protection method. The amount of slice registers utilized in the proposed system are 739 for Virtex 5, it is less when compared to the duplication with comparison based protection method.