RTL Level Implementation of High Speed-Low Power Viterbi Encoder & Decoder

被引：0
|
作者：
Singh, Pooran [1 ]
Vishvakarma, Santosh Kr [2 ]
机构：
[1] Indian Inst Technol IIT Indore, Sch Engn, Elect Engn Discipline, VLSI ULSI Circuit & Syst Design Lab, Indore 453441, Madhya Pradesh, India
[2] Indian Inst Technol, Sch Engn, Elect Engn Discipline, VLSI ULSI Circuit & Syst Design Lab, Indore, Madhya Pradesh, India
来源：
2013 INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE AND TECHNOLOGY (ICIST) | 2013年
关键词：
CONVOLUTIONAL-CODES;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
High speed and low power Viterbi Encoder Decoder of rate 1/2 convolutional coding with a constraint length K = 3 is presented in this paper. After implementation of proposed Viterbi encoder-decoder in Virtex 7 Field Programmable Gate Array (FPGA) kit we come to know that it's functioning on 393.544 MHz clock and in such a high speed it also maintain a low power of 11.34 mW in Spartan 6 FPGA. Since the FPGA boards used are different and from that we justified that using both logics together in one Integrated Circuit (IC) we can create a high speed and low power Viterbi encoder decoder at the same time with some extra hardware area.
引用
收藏
页码：345 / 349
页数：5
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