HySim: Hybrid fault simulation for synchronous sequential circuits

被引:0
|
作者
Kim, K [1 ]
Saluja, KK [1 ]
机构
[1] UNIV WISCONSIN,DEPT ELECT & COMP ENGN,MADISON,WI 53706
关键词
dynamic memory usage; converged fault detection; fault descriptor; fault simulation; hybrid fault simulation; HySim; synchronous sequential circuits;
D O I
10.1155/1996/72136
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The paper identifies the inefficiencies of the critical processes in concurrent fault simulation and proposes methods to remove such inefficiencies in a systematic manner. Also, proposed are dynamic memory usage reduction strategies for concurrent fault simulators. Through extensive step-by-step experimentation, we verified the effectiveness of the proposed methods for performance improvement and identified best memory management strategy for dynamic memory usage reduction. A simulator, HySim, based on the proposed methods is implemented and shown to outperform the existing fault simulators and achieve dramatic memory usage reduction. The HySim maintains fault lists which are subsets of that of a conventional concurrent fault simulator, which yields shorter fault list processing time and reduced dynamic memory usage. It also employs Release-and-Reconstruct method for fault list construction, where any fault list identified to be useless is released immediately. The experimental results show that Release-and-Reconstruct method is very effective in dynamic memory usage reduction.
引用
收藏
页码:181 / 197
页数:17
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