Logic Design of a 16-bit Bit-Slice Arithmetic Logic Unit for 32-/64-bit RSFQ Microprocessors

被引：16
|
作者：
Tang, Guang-Ming [1 ]
Qu, Pei-Yao [1 ]
Ye, Xiao-Chun [1 ]
Fan, Dong-Rui [1 ]
机构：
[1] Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China
来源：
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY | 2018年 / 28卷 / 04期
基金：
中国国家自然科学基金;
关键词：
Arithmetic logic unit (ALU); microprocessor; rapid single-flux-quantum (RSFQ); superconducting integrated circuits; FLUX-QUANTUM MICROPROCESSOR; SFQ MICROPROCESSOR; IMPLEMENTATION;
D O I：
10.1109/TASC.2018.2799994
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 16-bit bit-slice arithmetic logic unit (ALU) is proposed for 32-/64-bit rapid single-flux-quantum microprocessors. It is based on a Ladner-Fischer adder. The ALU covers all of the ALU operations for MIPS32 instructions set. And each of the two 64-bit operands is dividedinto four slices of 16 bits each. The ALU uses synchronous concurrent-flow clocking and consists of 11 pipeline stages. The proposed ALU can be used for any 16n-bit processing.
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页数：5
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