An efficient crossover architecture for hardware parallel implementation of genetic algorithm

被引：25
|
作者：
Faraji, Rasoul [1 ]
Naji, Hamid Reza [1 ]
机构：
[1] Grad Univ Adv Technol, Dept Elect & Comp Engn, Haftbagh BLV, Kerman, Iran
来源：
NEUROCOMPUTING | 2014年 / 128卷
关键词：
Genetic algorithm; FPGA; Crossover operator; PERFORMANCE; OPTIMIZATION;
D O I：
10.1016/j.neucom.2013.08.035
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this article a new architecture for hardware implementation of genetic algorithm in reconfigurable embedded systems is presented. The main idea is based on the efficient use of a genetic algorithm's crossover operator to enhance the speed of algorithm to reach an optimal solution. In this article a new crossover called DSO and also two new architectures for implementation of crossover operators are introduced to provide suitable solutions for solving the problems related to fitness function of the genetic algorithm. At first, some optimum operators are selected and then utilized in a new parallel architecture to increase the speed and accuracy of algorithm convergence. Finally, based on reusability of existing resources, the main idea of the article is introduced to improve the performance of the algorithm and finding the optimal solution. The properties of FPGAs such as flexibility and parallelism help this purpose. Crown Copyright (C) 2013 Published by Elsevier B.V. All rights reserved.
引用
收藏
页码：316 / 327
页数：12
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