Hardware implementation of AES based on genetic algorithm

被引：0
|
作者：
Wang, Li [1 ]
Wang, Youren [1 ]
Yao, Rui [1 ]
Zhang, Zhai [1 ]
机构：
[1] Nanjing Univ Aeronaut & Astronaut, Coll Automat Engn, Nanjing 210016, Jiangsu, Peoples R China
来源：
ADVANCES IN NATURAL COMPUTATION, PT 2 | 2006年 / 4222卷
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The high performance cryptographic chip is the core unit of the network information safety equipments. This paper proposes the design approach of the AES cryptographic system based on reconfigurable hardware, develops the method of key-sequence generation with the genetic algorithm that realizes different cipher key in every encryption round. The system has been implemented on Virtex-E FPGA. The result proves that the new design technology is feasible, and the security level of the AES is improved.
引用
收藏
页码：904 / 907
页数：4
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