The hardware implementation of a genetic algorithm model with FPGA

被引：3
|
作者：
Tu, L [1 ]
Zhu, MC [1 ]
Wang, JX [1 ]
机构：
[1] Shenzhen Univ, EDA Technol Ctr, Shenzhen 518060, Peoples R China
来源：
2002 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS | 2002年
关键词：
genetic algorithm (GA); FPGA; hardware implementation;
D O I：
10.1109/FPT.2002.1188714
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A genetic algorithm (GA) is a robust parallel calculation method based on natural selection, which can be applied to the distributed and concentrated industry optimizing control process. The hardware function of GA operation can be implemented by FPGA. In this paper, a hardware implementation method of GA based on FPGA is presented. The results of this research can be applied to the study and implementation of evolvable hardware (EHW).
引用
收藏
页码：374 / 377
页数：4
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