A Stepwise Dimension Reduction Approach to Evolutionary Design of Relative Large Combinational Logic Circuits

被引：0

作者：

Li, Zhifang ^{[1
]}

Luo, Wenjian ^{[1
]}

Wang, Xufa ^{[1
]}

机构：

[1] Univ Sci & Technol China, Dept Comp Sci & Technol, Nat Inspired Computat & Applicat Lab, Hefei 230027, Anhui, Peoples R China

来源：

EVOLVABLE SYSTEMS: FROM BIOLOGY TO HARDWARE, PROCEEDINGS | 2008年 / 5216卷

关键词：

Evolvable Hardware; Evolutionary Algorithm; Combinational Logic Circuits;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, a stepwise dimension reduction (SDR) approach to evolutionary design of relatively large combinational logic circuits is proposed. The proposed method divides the whole circuit into several layers. As for a circuit with one output, the number of input combinations is expected to be reduced layer-by-layer. The current layer's outputs are the next layer's inputs. All layers are evolved separately one after another, and assembled to form a final solution. The experimental results of SDR on parities, multipliers and circuits taken from MCNC library are comparable with those of GDD. Especially, the 19-parity circuit can be evolved successfully.

引用

页码：47 / 58

页数：12

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