共 50 条
- [1] Design of Subthreshold Adiabatic Logic based Combinational and Sequential Circuits [J]. 2017 INTERNATIONAL CONFERENCE ON EMERGING TRENDS & INNOVATION IN ICT (ICEI), 2017, : 9 - 14
- [2] Fault tolerant design of combinational and sequential logic based on a parity check code [J]. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2003, : 563 - 570
- [5] COMBINATIONAL LOGIC DESIGN WITH DECODERS [J]. IEEE TRANSACTIONS ON COMPUTERS, 1978, 27 (09) : 869 - 875
- [9] Design of combinational logic circuits through an evolutionary multiobjective optimization approach [J]. AI EDAM-ARTIFICIAL INTELLIGENCE FOR ENGINEERING DESIGN ANALYSIS AND MANUFACTURING, 2002, 16 (01): : 39 - 53
- [10] A solution for combinational and asynchronous sequential logic problems by means of logic variable [J]. 42ND IEEE CONFERENCE ON DECISION AND CONTROL, VOLS 1-6, PROCEEDINGS, 2003, : 3227 - 3232