Design of combinational logic digital circuits using a mixed logic synthesis method

The main contribution of this paper is the proposition of a technology independent low power synthesis procedure at the logic (gate) level for combinational logic digital CMOS circuits without reconvergent fan-out nodes, implementing Adjacent and/or Non-Adjacent Boolean functions. While many papers have been published describing power-saving techniques, trade-off's between the different design metrics are rarely discussed. In this paper, this issue is being addressed by means of a combined optimization parameter viz, Figure of Merit (FoM), for evaluating the quality of logic circuits designed. The goal is to decrease the power consumption and simultaneously improve the overall Figure of Merit. Since the power dissipated by a combinational logic circuit is mainly dictated by the switching activities of all signals associated with the circuit, the main focus has been on reducing the signal activities to the minimal level required A novel mathematical formulation has also been developed for a unique classification of gates. Experimental results obtained on the basis of the proposed strategy for 0.5-mu m CMOS technology, report minimization in average power consumption by about 36.1%, along with a substantial improvement in FoM to the tune of nearly 45.7%, on an average.