A Modified ESD Clamp Circuit for 90-nm CMOS Process

被引：0
|
作者：
Liu, Hong-Xia [1 ]
Yang, Zhao-Nian [1 ]
Luo, Yi [2 ]
Liu, Chen [2 ]
机构：
[1] Xidian Univ, Sch Microelect, Key Lab, Minist Educ Wide Band Gap Semicond Mat & Devices, Xian 710071, Peoples R China
[2] Xian Semipower Elect Technol Co, Xian 710075, Peoples R China
来源：
2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012) | 2012年
基金：
中国国家自然科学基金;
关键词：
DESIGN;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In nanoscale CMOS process, integrated circuits (ICs) face serious gate reliability issues such as the damage of electrostatic discharge (ESD). The RC-triggered silicon-controlled rectifier (SCR) is widely studied for the high turn-on efficiency and discharge capability. However, the large gate leakage current of MOS capacitor in the traditional RC network in nanoscale process is not desired. In this work, a modified detection circuit with feedback technique is proposed. The leakage current is reduced to 16 nA at room temperature (25 degrees C). Under the ESD event, it injects 38 mA trigger current into the p-substrate of SCR. Compared with the previous circuits, the proposed circuit can save area and power consumption while achieving the same performance. The simulation result shows that this clamp circuit can be used in industry.
引用
收藏
页码：872 / 875
页数：4
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