On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process

被引：0

作者：

Ker, Ming-Dou ^{[1
,2
]}

Chiu, Po-Yen ^{[2
]}

Tsai, Fu-Yi ^{[3
]}

Chang, Yeong-Jar ^{[3
]}

机构：

[1] I Shou Univ, Dept Elect Engn, Kaohsiung, Taiwan

[2] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30050, Taiwan

[3] Faraday Technol Corp, Hsinchu, Taiwan

来源：

ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 | 2009年

关键词：

PROTECTION DESIGN;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25 degrees C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.

引用

页码：2281 / +

页数：2

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