Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process

被引：8

作者：

Chiu, Po-Yen ^{[1
]}

Ker, Ming-Dou ^{[1
,2
]}

Tsai, Fu-Yi ^{[3
]}

Chang, Yeong-Jar ^{[3
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30039, Taiwan

[2] I Shou Univ, Dept Elect Engn, Kaohsiung, Taiwan

[3] Faraday Technol Corp, Hsinchu, Taiwan

来源：

2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2 | 2009年

关键词：

electrostatic discharge (ESD); ESD clamp circuit; gate leakage; silicon-controlled rectifier (SCR); PROTECTION DESIGN;

D O I：

10.1109/IRPS.2009.5173343

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25 degrees C, which is much smaller than that (613 mu A) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

引用

页码：750 / +

页数：2

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