All-nMOS Power-Rail ESD Clamp Circuit With Compact Area and Low Leakage

被引：0
|
作者：
Hsieh, Chia-You [1 ]
Lin, Chun-Yu [2 ]
机构：
[1] Natl Taiwan Normal Univ, Dept Elect Engn, Taipei 106308, Taiwan
[2] Natl Yang Ming Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2024年 / 71卷 / 09期
关键词：
Electrostatic discharges; MOS devices; Monitoring; Stress; Clamps; Temperature measurement; Electrostatic discharge protection; All-nMOS; area-effective; electrostatic discharge (ESD); low leakage; PROTECTION; DESIGN; VOLTAGE;
D O I：
10.1109/TED.2024.3434776
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
ICs are susceptible to breakage due to electrostatic discharge (ESD), making ESD protection circuits necessary for ICs. In some applications, internal circuits may adopt an all n-type transistor design. In such cases, the ESD protection circuit should only use n-type transistors to reduce the number of process masks required. This work proposes both a basic and an improved design for an all-nMOS power-rail ESD clamp. The improved design uses a current mirror circuit and nMOS string to reduce chip area and leakage, respectively. These ESD protection circuits have been implemented and validated in a 0.18- $\mu $ m CMOS process. The proposed designs are cost-effective and offer higher ESD robustness for practical applications.
引用
收藏
页码：5205 / 5211
页数：7
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