New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process

被引：11
|
作者：
Ker, Ming-Dou [1 ,2 ]
Chiu, Po-Yen [1 ]
机构：
[1] Natl Chiao Tung Univ, Inst Elect, Nanoelect & Gigascale Syst Lab, Hsinchu 300, Taiwan
[2] I Shou Univ, Dept Elect Engn, Kaohsiung 84001, Taiwan
来源：
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2011年 / 11卷 / 03期
关键词：
Electrostatic discharge (ESD); gate leakage; power-rail ESD clamp circuit; substrate-triggered silicon-controlled rectifier (STSCR); PROTECTION DESIGN;
D O I：
10.1109/TDMR.2010.2066976
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with consideration of the gate leakage issue has been proposed and verified in a 65-nm low-voltage CMOS process. Consisting of the new low-leakage ESD-detection circuit and the ESD clamp device of a substrate-triggered silicon-controlled rectifier, the new proposed power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has a very low leakage current of only 116 nA at room temperature (25 degrees C) under the power-supply voltage of 1 V. Moreover, the new proposed power-rail ESD clamp circuit can achieve ESD robustness of over 8 kV, 800 V, and over 2 kV in human-body-model, machine-model, and charged-device-model ESD tests, respectively.
引用
收藏
页码：474 / 483
页数：10
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