Power-Rail ESD Clamp Circuit with Embedded-Trigger SCR Device in a 65-nm CMOS Process

被引：0

作者：

Altolaguirre, Federico A. ^{[1
]}

Ker, Ming-Dou ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Nanoelect & Gigascale Syst Lab, Hsinchu 30039, Taiwan

来源：

2014 IEEE 57TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2014年

关键词：

PROTECTION DESIGN;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

SCR is the preferred ESD protection device in nanoscale CMOS technologies due to the better area efficiency compared the BIGFET, virtually no leakage current and smaller capacitance. The main drawback of the SCR is the slow turn-on speed, which is solved by adding dummy gates to block the STI formations inside the SCR structure. This work demonstrates that the dummy gate inside the SCR can be effectively used as an embedded trigger transistor, eliminating the need of an external trigger transistor in the ESD protection circuit and so further reducing silicon area and standby leakage current.

引用

页码：250 / 253

页数：4

共 50 条

[1] Area-Efficient Power-Rail ESD Clamp Circuit with SCR Device Embedded into ESD-Transient Detection Circuit in a 65nm CMOS Process
Yeh, Chih-Ting
Ker, Ming-Dou
[J]. 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
[2] Area-Efficient Power-Rail ESD Clamp Circuit with SCR Device Embedded into ESD-Transient Detection Circuit in a 65nm CMOS Process
Yeh, Chih-Ting
Ker, Ming-Dou
[J]. 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
[3] Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process
Lu, Guangyi
Wang, Yuan
Zhang, Lizhong
Cao, Jian
Zhang, Xing
[J]. SCIENCE CHINA-INFORMATION SCIENCES, 2016, 59 (12)
[4] Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process
Guangyi LU
Yuan WANG
Lizhong ZHANG
Jian CAO
Xing ZHANG
[J]. Science China(Information Sciences), 2016, 59 (12) : 170 - 178
[5] Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technology
Altolaguirre, Federico A.
Ker, Ming-Dou
[J]. 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
[6] Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technology
Altolaguirre, Federico A.
Ker, Ming-Dou
[J]. 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
[7] 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Low Standby Leakage in 65-nm CMOS Process
Lin, Chun-Yu
Ker, Ming-Dou
[J]. 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 3417 - 3420
[8] New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process
Ker, Ming-Dou
Chiu, Po-Yen
[J]. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2011, 11 (03) : 474 - 483
[9] Power-rail ESD Clamp Circuit with Hybrid-detection Enhanced Triggering in a 65-nm, 1.2-V CMOS Process
Lu, Guangyi
Wang, Yuan
Wang, Yize
Zhang, Xing
[J]. 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017, : 589 - 592
[10] Low-Leakage Power-Rail ESD Clamp Circuit With Gated Current Mirror in a 65-nm CMOS Technology
Aliolaguirre, Federico A.
Keri, Ming-Dou
[J]. 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 2638 - 2641

← 1 2 3 4 5 →