All-nMOS Power-Rail ESD Clamp Circuit With Compact Area and Low Leakage

被引：0

作者：

Hsieh, Chia-You ^{[1
]}

Lin, Chun-Yu ^{[2
]}

机构：

[1] Natl Taiwan Normal Univ, Dept Elect Engn, Taipei 106308, Taiwan

[2] Natl Yang Ming Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2024年 / 71卷 / 09期

关键词：

Electrostatic discharges; MOS devices; Monitoring; Stress; Clamps; Temperature measurement; Electrostatic discharge protection; All-nMOS; area-effective; electrostatic discharge (ESD); low leakage; PROTECTION; DESIGN; VOLTAGE;

D O I：

10.1109/TED.2024.3434776

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

ICs are susceptible to breakage due to electrostatic discharge (ESD), making ESD protection circuits necessary for ICs. In some applications, internal circuits may adopt an all n-type transistor design. In such cases, the ESD protection circuit should only use n-type transistors to reduce the number of process masks required. This work proposes both a basic and an improved design for an all-nMOS power-rail ESD clamp. The improved design uses a current mirror circuit and nMOS string to reduce chip area and leakage, respectively. These ESD protection circuits have been implemented and validated in a 0.18- $\mu $ m CMOS process. The proposed designs are cost-effective and offer higher ESD robustness for practical applications.

引用

页码：5205 / 5211

页数：7

共 50 条

[31] Area-efficient Power-rail ESD Clamp Circuit with False-trigger Immunity in 28nm CMOS Process
Shen, Zilong
Wang, Yize
Zhang, Xing
Wang, Yuan
6TH IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2022), 2022, : 271 - 273
[32] A low leakage power-rail ESD detection circuit with a modified RC network for a 90-nm CMOS process
杨兆年
刘红侠
王树龙
JournalofSemiconductors, 2013, 34 (04) : 116 - 120
[33] Study and validation of a power-rail ESD clamp in BiCMOS process with a reduced temperature dependency of its leakage current
Barbier, F
Blanc, F
Le Grontec, A
Colclaser, R
Smedes, T
Johnson, M
Bardy, S
Descamps, P
MICROELECTRONICS RELIABILITY, 2004, 44 (9-11) : 1799 - 1804
[34] Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
Yeh, Chih-Ting
Ker, Ming-Dou
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (11) : 2476 - 2486
[35] Power-Rail ESD Clamp Circuit with Polysilicon Diodes Against False Trigger During Fast Power-on Events
Chen, Jie-Ting
Ker, Ming-Dou
2018 40TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2018,
[36] Area-Efficient Power-Rail ESD Clamp Circuit With False-Trigger Immunity in 28nm CMOS Process
Shen, Zilong
Wang, Yize
Zhang, Xing
Wang, Yuan
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2022, 10 : 876 - 884
[37] A Prolonged Discharge Time ESD Power-rail Clamp Circuit Structure with Strong Ability to Prevent False Triggering
Cao, Jian
Xue, Xiangxiang
Wang, Yuan
Lu, Guangyi
Zhang, Xing
2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2016, : 1291 - 1293
[38] Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity
Lu, Guangyi
Wang, Yuan
Zhang, Lizhong
Wang, Yize
Huang, Ru
Zhang, Xing
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
[39] Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
Wang, Chang-Tzu
Ker, Ming-Dou
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (06) : 1460 - 1465
[40] Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process
Ker, MD
Lo, WY
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (04) : 601 - 611

← 1 2 3 4 5 →