Gate-all-around MOSFETs:: lateral ultra-narrow (≤10nm) fin as channel body

被引:6
|
作者
Singh, N [1 ]
Agarwal, A [1 ]
Bera, LK [1 ]
Kumar, R [1 ]
Lo, GQ [1 ]
Narayanan, B [1 ]
Kwong, DL [1 ]
机构
[1] Inst Microelect, Singapore 117685, Singapore
关键词
D O I
10.1049/el:20053195
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The fabrication of lateral ultra-narrow fin body (thickness <= 10 nm) gate-all-around MOSFETs. which exhibit excellent gate electrostatic control over the channel. is presented. The narrow fins were formed using alternating phase DUV lithography and low temperature oxidation of Si. The device characteristics are completely free from substrate bias effects.
引用
收藏
页码:1353 / 1354
页数:2
相关论文
共 50 条
  • [1] Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
    Bangsaruntip, S.
    Balakrishnan, K.
    Cheng, S. -L.
    Chang, J.
    Brink, M.
    Lauer, I.
    Bruce, R. L.
    Engelmann, S. U.
    Pyzyna, A.
    Cohen, G. M.
    Gignac, L. M.
    Breslin, C. M.
    Newbury, J. S.
    Klaus, D. P.
    Majumdar, A.
    Sleight, J. W.
    Guillorn, M. A.
    2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,
  • [2] Performance Evaluation of Stacked Gate-All-Around MOSFETs at 7 and 10 nm Technology Nodes
    Wu, Meng-Yen
    Chiang, Meng-Hsueh
    PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016, 2016, : 169 - 172
  • [3] Characterictics Variability of Gate-All-Around Polycrystalline Silicon Nanowire Transistors with Width 10nm Scale
    Jang, Ki-Hyun
    Saraya, Takuya
    Kobayashi, Masaharu
    Sawamoto, Naomi
    Gura, Atsushi
    Hiramoto, Toshiro
    2017 SILICON NANOELECTRONICS WORKSHOP (SNW), 2017, : 33 - 34
  • [4] Ultra-narrow silicon nanowire Gate-All-Around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance
    Singh, N.
    Lim, F. Y.
    Fang, W. W.
    Rustagi, S. C.
    Bera, L. K.
    Agarwal, A.
    Tung, C. H.
    Hoe, K. M.
    Omampuliyur, S. R.
    Tripathi, D.
    Adeyeye, A. O.
    Lo, G. Q.
    Balasubramanian, N.
    Kwong, D. L.
    2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 294 - +
  • [5] Mobility Enhancement over Universal Mobility in (100) Silicon Nanowire Gate-All-Around MOSFETs with Width and Height of Less Than 10nm Range
    Chen, Jiezhi
    Saraya, Takuya
    Hiramoto, Toshiro
    2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, : 175 - 176
  • [6] Standard Cell Library Based Layout Characterization and Power Analysis for 10nm Gate-All-Around (GAA) Transistors
    Wang, Luhao
    Cui, Tiansong
    Nazarian, Shahin
    Wang, Yanzhi
    Pedram, Massoud
    2016 29TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2016, : 253 - 258
  • [7] Modeling, verification and comparison of short-channel double gate and gate-all-around MOSFETs
    Kolberg, S.
    Borli, H.
    Fjeldly, T. A.
    MATHEMATICS AND COMPUTERS IN SIMULATION, 2008, 79 (04) : 1107 - 1115
  • [8] Tellurium Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications
    Yin, Yiheng
    Zhang, Zhaofu
    Zhong, Hongxia
    Shao, Chen
    Wan, Xuhao
    Zhang, Can
    Robertson, John
    Guo, Yuzheng
    ACS APPLIED MATERIALS & INTERFACES, 2021, 13 (02) : 3387 - 3396
  • [9] Design Optimization of 10 nm Channel Length InGaAs Vertical Gate-All-Around Transistor (Nanowire)
    Kulkarni, Shreyas
    Joshi, Sangeeta
    Bade, Dattatray
    Subramaniam, Subha
    COMPUTING, COMMUNICATION AND SIGNAL PROCESSING, ICCASP 2018, 2019, 810 : 611 - 619
  • [10] A compact explicit DC model for short channel Gate-All-Around junctionless MOSFETs
    Lime, Francois
    Avila-Herrera, Fernando
    Cerdeira, Antonio
    Iniguez, Benjamin
    SOLID-STATE ELECTRONICS, 2017, 131 : 24 - 29