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- [1] Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond 2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,
- [2] Performance Evaluation of Stacked Gate-All-Around MOSFETs at 7 and 10 nm Technology Nodes PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016, 2016, : 169 - 172
- [3] Characterictics Variability of Gate-All-Around Polycrystalline Silicon Nanowire Transistors with Width 10nm Scale 2017 SILICON NANOELECTRONICS WORKSHOP (SNW), 2017, : 33 - 34
- [4] Ultra-narrow silicon nanowire Gate-All-Around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance 2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 294 - +
- [5] Mobility Enhancement over Universal Mobility in (100) Silicon Nanowire Gate-All-Around MOSFETs with Width and Height of Less Than 10nm Range 2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, : 175 - 176
- [6] Standard Cell Library Based Layout Characterization and Power Analysis for 10nm Gate-All-Around (GAA) Transistors 2016 29TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2016, : 253 - 258
- [9] Design Optimization of 10 nm Channel Length InGaAs Vertical Gate-All-Around Transistor (Nanowire) COMPUTING, COMMUNICATION AND SIGNAL PROCESSING, ICCASP 2018, 2019, 810 : 611 - 619