Design Optimization of 10 nm Channel Length InGaAs Vertical Gate-All-Around Transistor (Nanowire)

被引：0

作者：

Kulkarni, Shreyas ^{[1
]}

Joshi, Sangeeta ^{[1
]}

Bade, Dattatray ^{[1
]}

Subramaniam, Subha ^{[2
]}

机构：

[1] Vidyalankar Inst Technol, Mumbai, Maharashtra, India

[2] Shah & Anchor Kutchhi Engn Coll, Mumbai, Maharashtra, India

来源：

COMPUTING, COMMUNICATION AND SIGNAL PROCESSING, ICCASP 2018 | 2019年 / 810卷

关键词：

Vertical Gate-All-Around (VGAA); InGaAs; Nanowire; Synopsys; Sentaurus TCAD;

D O I：

10.1007/978-981-13-1513-8_62

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper proposes a cylindrical vertical Gate-All-Around Transistor with nanowire of compound III-V semiconductor material In0.53Ga0.47 As n-type device with channel length of 10 nm. The effect of variation of channel diameter and spacer length on the performance of the device is simulated. The device gives an acceptable Subthreshold Slope and Drain Induced Barrier Lowering along with satisfactory I-ON/I-OFF ratio. The device is simulated in Sentaurus Synopsys using Hydrodynamic model for III-V semiconductors with Poisson equation to give the transfer characteristics.

引用

页码：611 / 619

页数：9

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