Design and optimization considerations for bulk gate-all-around nanowire MOSFETs

In this paper, design and optimization considerations for bulk gate-all-around nanowire MOSFETs have been investigated based on calibrated three-dimensional quantum correction numerical simulation. As device parasitical parameters play a crucial role in the optimization of overall performance of nanoscale bulk nanowire MOSFETs, we have placed great emphasis on projecting insights into the design of parasitic grooved-gate transistor and the source/drain (S/D) extension region. Furthermore, taking several important electrical parameters such as V-th, I-on, I-off, subthreshold swing ( Ss) and drain-induced barrier lowering (DIBL) as scaling criteria, the scaling of gate dielectric oxide (t(ox)) and the diameter of nanowire (t(si)) is discussed. The request for a high-k gate dielectric could be postponed due to the novel advanced structure, and there exists an optimal t(si) for high performance application.