Performance Evaluation of Stacked Gate-All-Around MOSFETs at 7 and 10 nm Technology Nodes

被引：0

作者：

Wu, Meng-Yen ^{[1
]}

Chiang, Meng-Hsueh ^{[2
]}

机构：

[1] Natl Cheng Kung Univ, Inst Microelect, Tainan 701, Taiwan

[2] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 701, Taiwan

来源：

PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016 | 2016年

关键词：

Gate-all-around MOSFET; FinFET; scale length; SCALING THEORY; SOI;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Performance evaluation of stacked gate-all-around (GAA) MOSFETs on device scaling and performance benchmark against FinFETs based on scale length are presented. While stacked GAA technique provides higher current (per pitch), FinFET counterpart shows its advantage in intrinsic gate delay. Such advantage becomes even more significant toward smaller technology node. By adjusting the aspect ratio of GAA devices based on same scale length, the thinner rectangular GAA case allows more stacked layers than the square case at the same total height and hence provides higher current. However, comparable intrinsic speeds are predicted for both cases.

引用

页码：169 / 172

页数：4

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