Performance Evaluation of Stacked Gate Oxide/High K Spacers Based Gate All Around Device Architectures at 10 nm Technology Node

In this paper, we have done performance evaluation of different Gate All Around (GAA) FET device structures using gate-oxide stacking and spacers of different materials including dual and corner spacers. Different spacer materials used are high K dielectric materials like HfO2, Si3N4 and low k dielectric material SiO2. Technology node is 10 nm for all the structures. GAA-FET with high k dielectric HfO2 as spacer improved leakage current and has higher I-ON/I-OFF ratio but it seriously degraded device RF performance having higher parasitic capacitances, lower cutoff frequency f(T) and lower maximum oscillation frequency f(MAX). GAA-FET with high k dielectric spacers is not a good choice for RF applications especially for tuned RF amplifiers and oscillators. However, GAA-FET with gate-oxide stacking and dual/corner spacers are the best choice having higher drive current, reasonable leakage current, good transconductance and excellent RF performance at the same time. Drive current of dual spacer is 33.7% more than that of SiO2 spacer. Whereas, drive current of corner spacer is around 14.5% more than that of SiO2 spacer. Total gate capacitance C-gg for dual and corner spacer is higher by only 1.9% and 1.6% respectively than that of GAA-FET with low K spacer SiO2. Cut off frequency f(T) of GAA-FET with dual and corner spacer is less than that of GAA-FET with SiO2 spacer by only 0.9% and 0.6% respectively whereas f(MAX) of GAA-FET with dual and corner spacer is less than that of GAA-FET with SiO2 spacer by 4.2% and 4.1% respectively.