CMOS Analog Four-Quadrant Multiplier Free of Voltage Reference Generators

被引：3

作者：

Sobrinho de Sousa, Antonio Jose ^{[1
]}

de Andrade, Fabian ^{[2
]}

dos Santos, Hildeloi ^{[2
]}

Goncalves, Gabriele ^{[2
]}

Pereira, Maicon Deivid ^{[2
]}

Santana, Edson ^{[2
]}

Cunha, Ana Isabela ^{[2
]}

机构：

[1] Univ Fed Oeste Bahia, Dept Engn Eletr, Bom Jesus Da Lapa, BA, Brazil

[2] Univ Fed Bahia, Dept Engn Eletr, Salvador, BA, Brazil

来源：

2019 32ND SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2019) | 2019年

关键词：

CMOS analog multiplier; four-quadrant multiplier; analog signal processing; MOS-TRANSISTOR MODEL; LOW-POWER; CLASS-AB;

D O I：

10.1145/3338852.3339870

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. The circuit has voltage-mode inputs and a current-mode output and includes a signal application method that avoids voltage or current reference generators. Simulations have been accomplished for a CMOS 130 nm technology, featuring +/- 50 mV input voltage range, 60 mu W static power and -25 dB maximum THD. The active area is 346 mu m(2).

引用

页数：6

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