Noise-aware power optimization for on-chip interconnect

被引：0
|
作者：
Kim, Ki-Wook [1 ]
Jung, Seong-Ook [1 ]
Narayanan, Unni [1 ]
Liu, C.L. [1 ]
Kang, Sung-Mo [1 ]
机构：
[1] Univ of Illinois at Urbana-Champaign, Urbana, United States
来源：
Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers | 2000年
关键词：
Cross-coupling - Cycle-averaged power model;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：108 / 113
相关论文
共 50 条
  • [1] Noise-aware power optimization for on-chip interconnect
    Kim, KW
    Jung, SO
    Narayanan, U
    Liu, CL
    Kang, SM
    ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, : 108 - 113
  • [2] Noise-aware interconnect power optimization in domino logic synthesis
    Kim, KW
    Jung, SO
    Narayanan, U
    Liu, CL
    Kang, SM
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (01) : 79 - 89
  • [3] Noise-aware on-chip power grid considerations using a statistical approach
    Andersson, Daniel A.
    Svensson, Lars J.
    Larsson-Edefors, Per
    ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2008, : 663 - 669
  • [4] Noise-aware buffer planning for interconnect-driven floorplanning
    Li, SM
    Cherng, YH
    Chang, YW
    ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 423 - 426
  • [5] Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning
    Li, Katherine Shu-Min
    Ho, Yingchieh
    Chen, Liang-Bi
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2013, E96A (12) : 2467 - 2474
  • [6] On-Chip Crosstalk Noise Reduction Model using interconnect optimization Techniques
    Hunagund, P. V.
    Kalpana, A. B.
    ICSE: 2008 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2008, : 87 - +
  • [7] Leakage-aware interconnect for on-chip network
    Tsai, YF
    Narayaynan, V
    Xie, Y
    Irwin, MJ
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 230 - 231
  • [8] Global interconnect optimization in the presence of on-chip inductance
    Roy, Abinash
    Chowdhury, Masud H.
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 885 - 888
  • [9] Noise-Aware Multiple-Voltage Assignment for Gate-Level Power Optimization
    Yan, Jin-Tai
    Chen, Zhi-Wei
    Luo, Jos-Hua
    2008 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, 2008, : 337 - 340
  • [10] Variation aware intuitive clock gating to mitigate on-chip power supply noise
    Majumder, Alak
    Bhattacharjee, Pritam
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2018, 105 (09) : 1487 - 1500
12345