Variation aware intuitive clock gating to mitigate on-chip power supply noise

With the advent of semiconductor process technology, both the dynamic and static power consumption have become major concerns for the circuit designers. Though clock gating (CG) is a potentially accomplished technique to minimise the dynamic power, it generally fails to cut down the static power dissipation. To address the same, we have unveiled a new CG scheme incorporating leakage control transistor, which simultaneously curbs the static and dynamic power along with the alleviation of power supply noise (PSN) in silicon chips by smartly controlling the current ramp (di/dt) and average current i(t): the main contributors to PSN. The proposed CG does not only save average, dynamic and static power by 84.34%, 90.33% and 66.73%, respectively, but also reduces PSN by 84.44% with respect to its non-gated counterpart when simulated using Cadence Virtuoso (R) for 90 nm Generic Process Design Kit at a switching frequency of 5 GHz and power supply voltage of 1.1 V.