Noise-aware power optimization for on-chip interconnect

被引：3

作者：

Kim, KW ^{[1
]}

Jung, SO ^{[1
]}

Narayanan, U ^{[1
]}

Liu, CL ^{[1
]}

Kang, SM ^{[1
]}

机构：

[1] Univ Illinois, Coordinated Sci Lab, Urbana, IL 61801 USA

来源：

ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2000年

关键词：

D O I：

10.1109/LPE.2000.876766

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wiles, Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.

引用

页码：108 / 113

页数：6

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