Leakage-aware interconnect for on-chip network

被引：0

作者：

Tsai, YF ^{[1
]}

Narayaynan, V ^{[1
]}

Xie, Y ^{[1
]}

Irwin, MJ ^{[1
]}

机构：

[1] Penn State Univ, University Pk, PA 16802 USA

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes Our schemes achieve 10.13%-63.57% active leakage savings and 12.35%-95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.

引用

页码：230 / 231

页数：2

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