Leakage-aware adaptive routing for pipelined on-chip networks in ultra-deep sub-micron technologies

As semiconductor process technology continues to scale down to the ultra-deep sub-micron level, leakage power becomes a critical design constraint for on-chip networks (OCNs). Power gating is widely used to reduce the OCN leakage power; however, it does not work well with adaptive routing owing to its aggressive use of free links and router buffers to achieve high performance. In this paper, a novel leakage-aware adaptive routing algorithm to increase the power-gating effect by routing packets with minimal link activation is proposed. Experimental results show that the proposed algorithm effectively achieves a reduction in the overall network leakage power of up to 11.6% greater than the conventional adaptive routing algorithm, with a little sacrificing network bandwidth.