Efficient sorting architecture for radix-4 FFT in FPGA

被引：0
|
作者：
Wu, Wan-Leng [1 ]
Shao, Jie [1 ]
Xian, Chu-Hua [1 ]
机构：
[1] Coll. of Info. Sci. and Technol., Nanjing Univ. of Aero. and Astron., Nanjing 210016, China
来源：
Nanjing Hangkong Hangtian Daxue Xuebao/Journal of Nanjing University of Aeronautics and Astronautics | 2005年 / 37卷 / 02期
关键词：
Algorithms - Computer architecture - Fast Fourier transforms - Field programmable gate arrays - Mathematical models;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The novel sorting architecture of the fast Fourier transform (FFT) processor is presented based on radix-4 decimation-in-time algorithm. By combining both the pipeline and parallel schemes, the proposed radix-4 butterfly uses three real multipliers and nine real adders, which leads to reduce conventional multipliers by 75%. The processor based on field programmable gate array (FPGA) can operate at 100 MHz and calculate the 1024 floating-point complex FFT in 51.29 μs. So it satisfies the needs of both small area and high speed. Furthermore, since the sorting architecture can be easily upgraded for radix-8 or radix-16 FFT algorithm, and does not increase the clocks required for computing a radix-4 butterfly, it will be more efficient for the high radix.
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页码：222 / 226
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