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- [21] Implementation of a High Speed Low power DSP Co-Processor based on Clock gating and Vedic Mathematics 2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), VOL. 1, 2016, : 836 - 839
- [22] Design of a Low-Power ALU and Synchronous Counter Using Clock Gating Technique PROGRESS IN ADVANCED COMPUTING AND INTELLIGENT ENGINEERING, VOL 2, 2018, 564 : 511 - 518
- [23] Low Power Compression Utilizing Clock-Gating 2011 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2011,
- [24] Design of Low Power Shift Register Using Activity-Driven Optimized Clock Gating and Run-Time Power Gating 2014 INTERNATIONAL CONFERENCE ON GREEN COMPUTING COMMUNICATION AND ELECTRICAL ENGINEERING (ICGCCEE), 2014,
- [25] The Merged Clock Gating Architecture For Low Power Digital Clock Application On FPGA 2018 INTERNATIONAL CONFERENCE ON ADVANCED TECHNOLOGIES FOR COMMUNICATIONS (ATC), 2018, : 282 - 286
- [26] Timing-Aware Clock Gating of Pulsed-Latch Circuits for Low Power Design 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
- [27] Timing-Aware Clock Gating of Pulsed-Latch Circuits for Low Power Design 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
- [29] Enabling Concurrent Clock and Power Gating in an Industrial Design Flow DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2009, : 334 - 339
- [30] Distributed Clock Gating for Power Reduction of a Programmable Waveform Generator for Neural Stimulation 2012 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC), 2012, : 3878 - 3881