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- [2] Low-power implementations of DSP through operand isolation and clock gating ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 229 - 232
- [3] Low Power Design of Johnson Counter Using Clock Gating 2012 15TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY (ICCIT), 2012, : 510 - 517
- [4] Low power network processor design using clock gating 42ND DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2005, 2005, : 712 - 715
- [5] A clock-gating method for low-power LSI design PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98, 1998, : 307 - 312
- [6] Implementation of Clock-Gating Technology in Low Power IC Design 2011 INTERNATIONAL CONFERENCE ON COMPUTER, COMMUNICATION AND INFORMATION TECHNOLOGY (ICCCIT 2011), 2011, : 165 - 168
- [7] COMPARITIVE ANALYSIS OF VARIOUS LOW POWER CLOCK GATING DESIGN FOR ALU 2014 INTERNATIONAL CONFERENCE ON ELECTRONICS AND COMMUNICATION SYSTEMS (ICECS), 2014,
- [8] New Activity-Driven Clock Tree Design Methodology for Low Power Clock Gating 2017 6TH INTERNATIONAL SYMPOSIUM ON NEXT GENERATION ELECTRONICS (ISNE), 2017,
- [9] Low Power Sorters Using Clock Gating 2021 IEEE INTERNATIONAL SYMPOSIUM ON SMART ELECTRONIC SYSTEMS (ISES 2021), 2021, : 6 - 11