Implementation of Clock-Gating Technology in Low Power IC Design

被引：0

作者：

Gao, Shen ^{[1
]}

Chen, Qiliang ^{[1
]}

Bi, Bo ^{[1
]}

机构：

[1] Beijing Microelect Technol Inst, Beijing, Peoples R China

来源：

2011 INTERNATIONAL CONFERENCE ON COMPUTER, COMMUNICATION AND INFORMATION TECHNOLOGY (ICCCIT 2011) | 2011年

关键词：

clock-gating; low power; clock network; RTL Compiler;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

As the scale of the digital IC design is increasing, lower power becomes increasingly important. We expatiate on the realization method of the clock gating technology in SOC design with examples, by using the RTL Compiler of the Cadence Corporation. It is proved that the gated clock can reduce the chip's dynamic power consumption without increasing the layout design complexity or affecting the existing workflow. At the same time, the technology can also decrease the chip's area.

引用

页码：165 / 168

页数：4