COMPARITIVE ANALYSIS OF VARIOUS LOW POWER CLOCK GATING DESIGN FOR ALU

In attendance to two high-speed and low-power ALU cells designed with an unconventional internal logic structure, CMOS bootstrapped dynamic logic, latch free, latch based and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). Besides, this paper deals with the design of ALU Clock Gating circuits then its Low Power Arithmetic and Logic Unit that has been developed as part of low power processor design. Here comparison among all the ALU and its clocking circuits are reported as having a low PDP, in stipulations of power delay product and power consumption, the proposed logic style improves switching speed by boosting the gate source voltage of transistors along timing-critical signal paths. This style helps to minimizes power operating cost by allowing a single boosting circuit to be shared by complementary outputs. Post-layout simulations show that the proposed ALU's outperform existing counterparts.