Glitch minimization and low power FPGA routing algorithm

被引：0
|
作者：
Huang, Juan [1 ,2 ]
Yang, Haigang [1 ]
Li, Wei [1 ,2 ]
Tan, Yitao [1 ,2 ]
Cui, Xiuhai [1 ]
机构：
[1] System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
[2] Graduate University of Chinese Academy of Sciences, Beijing 100049, China
来源：
Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | 2010年 / 22卷 / 10期
关键词：
Cost functions - Routing algorithms - Table lookup;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
This paper describes a routing algorithm that limits the number of glitches in order to reduce dynamic power in FPGAs. The algorithm involves modifying cost function and aligning the arrival time of signals to the inputs of the lookup tables to filter out some glitches. During the same run time, experimental results demonstrate that the proposed method eliminates 23.4% of the glitches, reduces overall FPGA power by 5.4%, while, compared with the VPR, the critical-path delay only increases by 1% on average. Furthermore, the proposed method requires no additional hardware to reduce glitches.
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页码：1664 / 1670
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