Low-power FPGA using partially low swing routing architecture

被引：4

作者：

Matsumoto, Y ^{[1
]}

Masaki, A

机构：

[1] Okayama Univ, Grad Sch Nat Sci & Technol, Okayama 7008530, Japan

[2] Okayama Univ, Fac Engn, Okayama 7008530, Japan

来源：

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE | 2005年 / 88卷 / 11期

关键词：

FPGA; routing architecture; power consumption; voltage swing;

D O I：

10.1002/ecjc.20170

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Since about 60% of the power consumption in FPGA is in routing, it is most important to reduce the power consumption in routing in order to reduce the overall power consumption in FPGA. In previous research, the reduction of the voltage swing in interconnect routing has been attempted in order to reduce the ED product. In general, low voltage swing of routing degrades the operating speed. Hence, in the present research, a partial reduction of voltage swing in routing is proposed. Also, a routing tool is developed for appropriate routing in the routing architecture with partially reduced voltage swing. Experiments show that the power consumption in routing can be reduced by about 30% without degrading the operating speed if the voltage swing in about 70% of the routing is reduced to half. (c) 2005 Wiley Periodicals, Inc.

引用

页码：11 / 19

页数：9

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