Fundus image denoising using FPGA hardware architecture

被引:12
|
作者
Fredj, Amira Hadj [1 ]
Ben Abdallah, Mariem [1 ]
Malek, Jihene [1 ]
Azar, Ahmad Taher [2 ]
机构
[1] Monastir Univ, Elect & Microelect Lab, Monastir, Tunisia
[2] Benha Univ, Fac Comp & Informat, Banha, Egypt
关键词
SRAD filter; FPGA; field-programmable gate array; parallel architecture; retinal fundus image;
D O I
10.1504/IJCAT.2016.077791
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Image processing algorithms, implemented in hardware, have recently emerged as the most viable solution for improving the performance of image processing systems. In this paper, a version of an anisotropic diffusion technique is used to reduce noise from retinal images, namely Speckle Reducing Anisotropic Diffusion ( SRAD). The SRAD filter can improve images corrupted by multiplicative or additive noise, but it has been the most computationally complex and it has not been suitable for software implementation in real-time processing. In this paper, an efficient Field-Programmable Gate Array ( FPGA)-based implementation of the SRAD filter is presented to accelerate the processing time. A comparison of the most used classical suppression filters like Gaussian, Median, Perona and Malik anisotropic diffusion has been carried out. The experimental results reveal a 38x performance improvement over the original MATLAB implementation and a 1.33x performance improvement over the hardware implementation using the Xilinx System Generator tool.
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页码:1 / 13
页数:13
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