共 50 条
- [21] Accelerating SVD on reconfigurable hardware for image denoising ICIP: 2004 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOLS 1- 5, 2004, : 259 - 262
- [22] Hybrid technique for fundus image enhancement using modified morphological filter and denoising net JOURNAL OF SUPERCOMPUTING, 2024, 80 (09): : 13317 - 13340
- [23] Hardware/Software FPGA Architecture for Robotics Applications RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, 2009, 5453 : 27 - 38
- [24] A Hardware Architecture of Target Tracking System on FPGA PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND APPLICATION ENGINEERING (CSAE2018), 2018,
- [25] FPGA Hardware Architecture of the Steganographic ConText Technique 18TH INTERNATIONAL CONFERENCE ON ELECTRONICS, COMMUNICATIONS AND COMPUTERS (CONIELECOMP 2008), PROCEEDINGS, 2008, : 123 - 128
- [26] An efficient hardware accelerated design for image denoising using Extended Trilateral Filter 2016 2ND INTERNATIONAL CONFERENCE ON CONTROL, INSTRUMENTATION, ENERGY & COMMUNICATION (CIEC), 2016, : 202 - 206
- [27] Adaptive Reconfigurable Architecture for Image Denoising 2015 IEEE 29TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS, 2015, : 196 - 201
- [28] A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA using Chisel HCL 2018 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW 2018), 2018, : 214 - 217
- [29] Fault Tolerance in FPGA Architecture Using Hardware Controller-Design Approach 2009 INTERNATIONAL CONFERENCE ON ADVANCES IN RECENT TECHNOLOGIES IN COMMUNICATION AND COMPUTING (ARTCOM 2009), 2009, : 906 - +
- [30] Design of A Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA 2014 FIFTH INTERNATIONAL SYMPOSIUM ON ELECTRONIC SYSTEM DESIGN (ISED), 2014, : 68 - 72