A GLOBAL DELAY MODEL FOR DOMINO CMOS CIRCUITS WITH APPLICATION TO TRANSISTOR SIZING

Domino CMOS circuits have played important roles in the design of high‐speed VLSI chips such as 32‐bit microprocessors and their family chips. Many researchers have worked on the characterization of the delay time and optimal design of domino CMOS circuits using circuit simulators as the main CAD tools. This paper presents a global analytical delay model for an important class of domino CMOS circuits wherein a multitude of n‐channel transistors form a series connection. the new model is shown to predict the delay time from the precharging clock edge to the 0.5 VDD output level with less than 10% error as compared to that from SPICE simulation over the entire design space. the delay model has been applied efficiently to the design automation of domino CMOS circuits modules. Copyright © 1990 John Wiley & Sons, Ltd.