TRANSISTOR SIZING FOR LARGE COMBINATIONAL DIGITAL CMOS CIRCUITS

This article describes a new method to determine the device sizes of combinational digital CMOS circuits for an upper limit on the signal propagation delays. By modeling gate delay and area or power consumption of a circuit as a simple analytical function of the device sizes, transistor sizing can be stated as a standard nonlinear program. A new and efficient problem formulation with a complexity proportional to the circuit size is presented that allows the optimization of large circuits with reasonable effort. During the optimization a sequence of valid and improved circuit configurations is produced such that the optimization may be stopped prematurely while comparing different implementation alternatives.