DELAY OPTIMIZATION OF DIGITAL CMOS VLSI CIRCUITS BY TRANSISTOR REORDERING

被引：8
|
作者：
CARLSON, BS [1 ]
LEE, SJ [1 ]
机构：
[1] SUNY STONY BROOK,NSF,CTR DESIGN ANALOG DIGITAL INTEGRATED CIRCUITS,STONY BROOK,NY 11794
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1995年 / 14卷 / 10期
关键词：
D O I：
10.1109/43.466335
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper the effects of transistor reordering on the delay of CMOS digital circuits are investigated, and an efficient method which uses transistor reordering for the delay optimization of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect an layout area and power dissipation, The technique can be coupled with transistor sizing to achieve the desired improvement in circuit delay. Experimental results for benchmark circuits are given in 2.0, 1.2, and 0.8 mu m CMOS technologies. The average improvement in delay for the 20 benchmarks used in this paper is 9.1%.
引用
收藏
页码：1183 / 1192
页数：10
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