Optimizing CMOS circuits for low power using transistor reordering

被引：6
|
作者：
Musoll, E [1 ]
Cortadella, J [1 ]
机构：
[1] UNIV POLITECN CATALUNYA,DEPT COMP ARCHITECTURE,E-08071 BARCELONA,SPAIN
来源：
EUROPEAN DESIGN & TEST CONFERENCE 1996 - ED&TC 96, PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/EDTC.1996.494152
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：219 / 223
页数：5
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