Low power CMOS circuits with clocked power

被引：4
|
作者：
Wu, XW [1 ]
Pedram, M [1 ]
机构：
[1] Ningbo Univ, Inst Circuits & Syst, Ningbo 315211, Peoples R China
来源：
2000 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS: ELECTRONIC COMMUNICATION SYSTEMS | 2000年
关键词：
D O I：
10.1109/APCCAS.2000.913549
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design which adopts gradually changing power clock. We discuss the algebraic expressions and the corresponding properties of clocked power signals. A clocked CMOS gate structure is presented and the clocked combinational circuit design is analyzed. The PSPICE simulations demonstrate the low power characteristic of clocked CMOS circuits using trapezoidal power-clock.
引用
收藏
页码：513 / 516
页数：4
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