A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology

被引：0

作者：

Wang Wei ^{[1
]}

Huang Beiju ^{[1
]}

Dong Zan ^{[1
]}

Guo Weilian ^{[2
]}

Chen Hongda ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Semicond, State Key Lab Integrated Optoelect, Beijing 100083, Peoples R China

[2] Tianjin Polytech Univ, Sch Informat & Commun, Tianjin 300160, Peoples R China

来源：

JOURNAL OF SEMICONDUCTORS | 2010年 / 31卷 / 05期

基金：

中国国家自然科学基金; 国家高技术研究发展计划(863计划);

关键词：

MOS-NDR; CMOS; resonant tunneling diode; monostable-bistable transition logic element; flexible logic gate;

D O I：

10.1088/1674-4926/31/5/055007

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

A MOS-NDR (negative differential resistance) transistor which is composed of four n-channel metaloxide-semiconductor field effect transistors (nMOSFETs) is fabricated in standard 0.35 mu m CMOS technology. This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD (resonant tunneling diode) in current-voltage characteristics. At the same time it can realize a modulation effect by the third terminal. Based on the MOS-NDR transistor, a flexible logic circuit is realized in this work, which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor. It turns out that MOS-NDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.

引用

页码：055007 / 055007

页数：4

共 50 条

[1] A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology
王伟
黄北举
董赞
郭维廉
陈弘达
[J]. Journal of Semiconductors, 2010, 31 (05) : 102 - 105
[2] Logic circuit design based on MOS-NDR devices and circuits fabricated by CMOS process
Gan, KJ
Liang, DS
Hsiao, CC
Wang, SY
Chiang, FC
Tsai, CS
Chen, YH
Kuo, SH
Chen, CP
[J]. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, : 392 - 395
[3] Efficient realisation of MOS-NDR threshold logic gates
Nunez, J.
Avedillo, M. J.
Quintana, J. M.
[J]. ELECTRONICS LETTERS, 2009, 45 (23) : 1158 - 1159
[4] Investigation of MOS-NDR voltage controlled ring oscillator fabricated by CMOS process
Gan, Kwang-Jow
Liang, Dong-Shong
Hsiao, Chung-Chih
Tsai, Cher-Shiung
Chen, Yaw-Hwang
[J]. 2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS, 2005, : 825 - 827
[5] Design of multi-threshold threshold gate using MOS-NDR circuits suitable for CMOS process
Gan, Kwang-Jow
Huang, Chien-Hsiung
Yeh, Wen-Kuan
Guo, Chun-Yi
Lu, Jeng-Jong
[J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2018, 96 (03) : 409 - 416
[6] Design of multi-threshold threshold gate using MOS-NDR circuits suitable for CMOS process
Kwang-Jow Gan
Chien-Hsiung Huang
Wen-Kuan Yeh
Chun-Yi Guo
Jeng-Jong Lu
[J]. Analog Integrated Circuits and Signal Processing, 2018, 96 : 409 - 416
[7] Five-state logic using MOS-HBT-NDR circuit by standard SiGeBiCMOS process
Gan, Kwang-Jow
Liang, Dong-Shong
Tsai, Cher-Shiung
Chen, Yaw-Hwang
Wen, Chun-Ming
[J]. 2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 1476 - +
[8] Four-valued memory circuit designed by multiple-peak MOS-NDR devices and circuits
Liang, DS
Gan, KJ
Su, LX
Chen, CP
Hsiao, CC
Tsai, CS
Chen, YH
Wang, SY
Kuo, SH
Chiang, FC
[J]. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, : 78 - 81
[9] Four-valued memory circuit using three-peak MOS-NDR devices and circuits
Gan, K. -J.
Chen, Y. -H.
Tsai, C. -S.
Su, L. -X.
[J]. ELECTRONICS LETTERS, 2006, 42 (09) : 514 - 515
[10] DC Analysis of a MOS based NDR Circuit
Sarkar, Mili
Chowdhury, Sabarno
Chowdhury, Subhajit Dutta
Choudhuri, Chayanika Dhar
Das, Debarshi
Basu, Megha
[J]. 7TH IEEE ANNUAL INFORMATION TECHNOLOGY, ELECTRONICS & MOBILE COMMUNICATION CONFERENCE IEEE IEMCON-2016, 2016,

← 1 2 3 4 5 →