Four-valued memory circuit designed by multiple-peak MOS-NDR devices and circuits

被引：0
|
作者：
Liang, DS
Gan, KJ
Su, LX
Chen, CP
Hsiao, CC
Tsai, CS
Chen, YH
Wang, SY
Kuo, SH
Chiang, FC
机构：
来源：
Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes the design of a four-valued memory cell based on a three-peak MOS-NDR circuit. We connect three MOS-NDR devices in parallel that can create a three-peak current-voltage curve by suitably arranging the parameters. Due to its folding I-V characteristics, multiple -peak NDR device is a very promising device for multiple -valued logic application. This memory cell structure can be easily extended to implement more states in a memory circuit.
引用
收藏
页码：78 / 81
页数：4
相关论文
共 10 条
  • [1] Four-valued memory circuit using three-peak MOS-NDR devices and circuits
    Gan, K. -J.
    Chen, Y. -H.
    Tsai, C. -S.
    Su, L. -X.
    [J]. ELECTRONICS LETTERS, 2006, 42 (09) : 514 - 515
  • [2] Logic circuit design based on MOS-NDR devices and circuits fabricated by CMOS process
    Gan, KJ
    Liang, DS
    Hsiao, CC
    Wang, SY
    Chiang, FC
    Tsai, CS
    Chen, YH
    Kuo, SH
    Chen, CP
    [J]. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, : 392 - 395
  • [3] Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits
    Gan, Kwang-Jow
    Lu, Jeng-Jong
    Yeh, Wen-Kuan
    Chen, Yaw-Hwang
    Chen, Yan-Wun
    [J]. ENGINEERING SCIENCE AND TECHNOLOGY-AN INTERNATIONAL JOURNAL-JESTECH, 2016, 19 (02): : 888 - 893
  • [4] Novel voltage-controlled oscillator design by MOS-NDR devices and circuits
    Liang, DS
    Gan, KJ
    Hsiao, CC
    Tsai, CS
    Chen, YH
    Wang, SY
    Kuo, SH
    Chiang, FC
    Su, LX
    [J]. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, : 372 - 375
  • [5] Design of Four-valued Operation Circuits of Adder and Subtraction Based on Neuron MOS Transistor
    Wang, Pengjun
    Zhang, Yuejun
    [J]. 2009 ASIA-PACIFIC CONFERENCE ON INFORMATION PROCESSING (APCIP 2009), VOL 1, PROCEEDINGS, 2009, : 382 - 385
  • [6] Multiple-valued decoder using MOS-HBT-NDR circuit
    Gan, K. J.
    Liang, D. -S.
    Tsai, C. -S.
    Chen, Y. -H.
    Wen, C. -M.
    [J]. ELECTRONICS LETTERS, 2007, 43 (20) : 1092 - 1093
  • [7] Frequency multiplier design based on multiple-peak R-BJT-NDR devices fabricated by SiGe technology
    Liang, Dong-Shong
    Gan, Kwang-Jow
    Tu, Chun-Da
    Tsai, Cher-Shiung
    Chen, Yaw-Hwang
    [J]. SIXTEENTH BIENNIAL UNIVERSITY/GOVERNMENT/INDUSTRY MICROELECTRONICS SYMPOSIUM, PROCEEDINGS, 2006, : 221 - +
  • [8] Room-Temperature Multi-Peak NDR in nc-Si Quantum-Dot Stacking MOS Structures for Multiple Value Memory and Logic
    Qian Xin-Ye
    Chen Kun-Ji
    Huang Jian
    Wang Yue-Fei
    Fang Zhong-Hui
    Xu Jun
    Huang Xin-Fan
    [J]. CHINESE PHYSICS LETTERS, 2013, 30 (07)
  • [9] Room-Temperature Multi-Peak NDR in nc-Si Quantum-Dot Stacking MOS Structures for Multiple Value Memory and Logic
    钱昕晔
    陈坤基
    黄健
    王越飞
    方忠慧
    徐骏
    黄信凡
    [J]. Chinese Physics Letters., 2013, 30 (07) - 192
  • [10] Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications
    Shin, Sunhae
    Kim, Kyung Rok
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS, 2015, 54 (06)
1