Four-valued memory circuit using three-peak MOS-NDR devices and circuits

被引：12
|
作者：
Gan, K. -J. [1 ]
Chen, Y. -H. [1 ]
Tsai, C. -S. [1 ]
Su, L. -X. [1 ]
机构：
[1] Kun Shan Univ, Dept Elect Engn, 949 Da Wan Rd, Yung Kang 710, Tainan Hsien, Taiwan
来源：
ELECTRONICS LETTERS | 2006年 / 42卷 / 09期
关键词：
D O I：
10.1049/el:20063634
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A four-valued memory circuit using the three-peak MOS-NDR circuit as the driver and a current source as the load is demonstrated. The fabrication of the circuit is based on the standard 0.35 mu m CMOs process.
引用
收藏
页码：514 / 515
页数：2
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