A 400 MFLOPS FFT PROCESSOR VLSI ARCHITECTURE

We propose a single-chip 400-MFLOPS 2-D FFT processor VLSI architecture. This processor integrates 380,000 transistors in an area of 11.58 x 11.58 mm2 using 0.8-mu-m CMOS technology with a typical machine cycle time of 25 ns, and executes 2n x 2n point 2-D FFT in real time, e.g., 256 x 256 point FFT is executed in 14 ms. This excellent performance in terms of both speed and dynamic range makes the real-time processing practical for video as well as speech processing.